Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to read-only memory (ROM), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that is typically erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” The memory cells of a Flash memory array are typically arranged into a “NOR” architecture (each cell directly coupled to a bit line) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access). Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
One recent type of Flash memory is a nitride read only memory (NROM). NROM has some of the characteristics of Flash memory but does not require the special fabrication processes of a conventional Flash memory, thus NROM integrated circuits can be implemented using a standard CMOS process. Because of their unique device characteristics, some NROM memory cells can also store multiple data bits in each cell (typically two bits each).
FIG. 1 illustrates a cross-sectional view of a typical prior art NROM memory cell with a channel length, L. The cell is comprised of a control gate 100 formed on top of an oxide-nitride-oxide (ONO) layer. This layer is comprised of an oxide layer 101 on top of a nitride 103 layer upon which the charge is stored for the various states of the cell. In one embodiment, the cell has trapping areas 105 and 106 for storing two bits of data on the nitride layer 103. The nitride layer 103 is deposited on another oxide layer 104 that is on the substrate.
Two source/drain regions 109 and 111 are at either end of the gate 100. The source/drain regions 109 and 111 are connected by a channel area 110 between the two source/drain regions 109 and 111. The function of each source/drain region 109 or 111 (i.e., whether source or drain) depends upon which bit trapping area 105 or 106 is being read or written. For example, in a read operation, if the carrier is input at the left side source/drain region 111 and output from the right side region 109, the left side is the source 111 and the right side is the drain 109 and the data bit charge is stored on the nitride 103 at the source end 111 for bit trapping area 106.
As integrated circuit processing techniques improve, manufacturers try to reduce the feature sizes of the devices produced and thus increase the density of the IC circuits and memory arrays. In NROM memory arrays in particular, the channel length of the NROM memory cells that make up the memory array and spacing between memory cells in the strings have a large effect on the number of memory cells that can be placed in a given area and thus a direct impact on the density of the array and size of the resulting memory device. In addition, in many cases the feature sizes of the devices are limited by the device characteristics before the minimum feature size that the process is capable of is reached. In NROM devices in particular, as the channel length is reduced, a minimum size is typically reached that is primarily dictated by the device operational characteristics. FIG. 2 illustrates a typical prior art planar NROM device that has a channel length that is less than 100 nm. In this case, the channel length is so short that the trapping areas 205 and 206 of the two data bits/cell NROM device overlap. This overlap may cause data write and read errors.
A further problem in floating gate and NROM memory cell arrays is the issue of overerased memory cells. An NROM memory cell is structurally similar to a MOSFET transistor, with a control gate separated from a channel, source, and drain by an insulator. In addition, embedded in the insulator is an isolated trapping layer. As in a MOSFET transistor, current flows when the NROM memory cell/transistor is selected or activated, charge trapped on the trapping layer affects the amount of current flow in the NROM transistor, depending on its direction of operation (current flow in the channel), effectively raising or lowering its threshold in the direction of operation. In programming or erasing an NROM memory cell, charge is transported to or from the electrically insulated trapping layer of the NROM transistor. If too much charge is removed from the trapping layer of the NROM transistor/memory cell it will flow current in this direction of operation even when it is not selected. NROM transistors in this overerased state can affect current flow on shared bitlines and/or memory strings and thus potentially corrupt data read from other memory cells these common bitlines and/or memory strings.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and architecture for producing a more closely spaced and, thus, higher density NROM memory array without trapping area overlap and with improved overerasure handling properties.